This invention relates to a circuit arrangement with a power MOSFET and two Zener diodes the anodes of which are coupled to each other, whereby the cathode terminal of the first Zener diode is coupled to the gate terminal, and the cathode terminal of the second Zener diode is coupled to the source terminal of the power MOSFET.
This circuit is described, for example, in a paper entitled "Untersuchungen an einem neuen MOSFET Modul" by L. Lorenz, W. Schierz, H. Amann, 3rd International Macroelectronics Conference, Munich, Nov. 13, 1986, pages 68 to 84. The circuit is illustrated in FIG. 1. Two Zener diodes 3 and 4 are connected between gate terminal G and source terminal S of a power MOSFET 1. They protect the gate-source capacitance of MOSFET 1 against excessive positive and negative voltages.
If MOSFET 1 is connected in series with a load 2 at the source end, then the gate-source voltage U.sub.GS must be higher than the supply voltage V.sub.BB in order to safely make MOSFET 1 conducting. If Zener diodes 3 and 4 are integrated into a common substrate, it cannot be assured that MOSFET 1 will be made conducting. The current versus voltage characteristic of I.sub.GS vs. U.sub.GS then has the shape illustrated in FIG. 2. With an increase in current I.sub.GS the voltage U.sub.GS first increases to the value of the Zener voltage of Zener diode 3 plus the forward voltage of Zener diode 4, e.g., to 6.7 volts. With a further increase in current the voltage drops back to a value of 4 V, for example, and then increases again only when there is a higher current. However, MOSFET 1 frequently cannot be rendered completely conducting with a voltage of 4 V.
The characteristic shown here is produced by switching on the parasitic bipolar transistor associated with Zener diode 3.
This behavior will now be explained with reference to FIG. 3. Zener diodes 3 and 4 includes a region 11 embedded in a semiconductor substrate 10 and zones 12 and 13 which are embedded in region 11. Region 11 as well as zones 12 and 13 are highly doped. Both Zener diodes have a parasitic bipolar transistor formed by zones 13, 11, 10 and 12, 11, 10. The parasitic npn bipolar transistor associated with Zener diode 3 is symbolically illustrated in this figure as transistor 14. If a positive potential which is required to switch on power MOSFET 1 and which must always be higher than the source potential is applied to gate terminal G, the collector of the parasitic bipolar transistor 14 is formed by zone 12, its base is formed by region 11 and its emitter is formed by substrate 10. The base of bipolar transistor 14 can float at a potential higher than the drain potential. Then the parasitic bipolar transistor 14 is rendered conducting and the full voltage cannot build up on Zener diode 3.